1. Field of the Invention
This invention relates to superconductive Josephson junction logic circuits. More particularly, the circuit relates to an improved logic OR gate circuit for performing logic functions.
2. Description of the Prior Art
This invention is an improvement of Josephson junction superconductive circuits of the type designed to be implemented as logic elements on large scale integrated (LSI) or very large scale integrated (VLSI) circuits. More particularly, the present invention is an improvement of U.S. Pat. No. 4,051,393 examined in Class 307, subclass 306. This prior art patent teaches a superconductive circuit having two parallel branches with an appropriately terminated output. Each of the two parallel branches contain one Josephson junction and the input to output loop circuit contains at least one resistor which provides appropriate input biasing and also improves the dynamic characteristics of the circuit by damping out undesired resonances. This prior art circuit provides modest gain and modest fan-out. For practical purposes, the gain of this circuit is less than two, thus, is not useful for more than one fan-out drive line.
An improved circuit of the above-basic patent is shown in IEEE, Transactions on Magnetics, Volume 15, No. 6, November 1979 at pages 1876-1879. This prior art circuit has been referred to as the Josephson Atto-Weber Switch (JAWS). This circuit employs two branches wherein one of the branches has a single Josephson junction and the other branch has a Josephson junction with a resistor. This article at FIG. 1 illustrates a two input logic driver which employs two power supplies and shows multiple output load resistors. This circuit has been examined and the gain at the output load is insufficient to drive more than one identical logic element with any margin of safety.
A further improvement of the above basic circuit shown in this application at FIG. 1, is disclosed in IEEE, International Electron Devices meeting, Washington, D.C., Dec. 3-5, 1979 at pages 482-484. This Josephson junction circuit has been referred to as Josephson Direct Coupled Logic or DCL and comprises an improvement over JAWS in that it includes a second resistor in the second or output branch which enables the circuit to be operated on one power supply rather than two. This basic device is employed as a logic module building block such as an OR and AND gate as in the present invention to be described more fully hereinafter. This DCL circuit provides the same output power as JAWS and is also insufficient to drive more than one identical logic element with any margin of safety.
Accordingly, it would be desirable to provide a new and novel Josephson junction circuit which can be used as a logic module building block. The novel module building block should be capable of having multiple inputs and also be capable of driving identical multiple outputs with a margin of safety.